978-620-0-47340-0

Low Power and Area Efficient 1024-Point FFT Processors

Using Power Radix with 4-Path Data Processing

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Summary:

The Fast Fourier transform (FFT) algorithm with radix-2k is used to accomplish both a radix-2 butterfly and a minimize number with twiddle factor multiplication as Radix-2k delay feedback and radix-K delay commutators are the major well-known pipeline architecture for FFT design. To reduce the memory and area requirement here in this thesis we implemented a novel radix-24 multiple delay commutators called 4-Path Feedforward FFT architecture utilizes the advantage of the radix-2 algorithm. By Combining the advantages of Radix-2 algorithm and feed-forward architecture, the proposed 4-Path radix-24 FFT processor achieves the least hardware requirement of multipliers and power consumption also reduced more when compared with Dual-path Radix-22 delay feedback FFT architecture. The entire FFT algorithms were implemented in Verilog hardware description language and synthesized with Xilinx IЅΕ design suit.

Author:

Dupakuntla Vishnu Vardhan

Biographie:

Dr. D. Vishnu Vardhan received Ph.D Degree from JNTU Anantapur, Ananthapuramu. Currently working as an Assistant Professor in the Department of ECE, JNTUACE, Ananthapuramu. Research interest includes Signal Processing, VLSI and Embedded Systems.Mr. K. Balaji is pursuing M.Tech.Degree in JNTUACE, Ananthapuramu.

Author:

Kunati Balaji

Biographie:

Number of Pages:

68

Book language:

English

Published On:

2019-12-04

ISBN:

978-620-0-47340-0

Publishing House:

LAP LAMBERT Academic Publishing

Keywords:

signal processing, FFT

Product category:

TECHNOLOGY / Electronics / General