Reed Solomon is the emerging algorithm that is going to be widely used in the future for the detection and correction of multibit errors in various applications like semiconductor memory, high speed and high-density disk drives, mobile communication, digital communication, and reliable data transmission. This is the focus work for my dissertation to implement RS encoder and decoder that is a complex algorithm and it is used for reliable memory operation in a system. Literature surveys were carried out to understand this complex algorithm because we could not get all the materials in one place so it needs a compilation of work. More than 2000 lines of RTL codes were developed in Verilog HDL under this dissertation work to realize this hardware module, nowhere such codes are available in the public domain on open-source codes on the internet. SRAMs are the one application area for RS decoder for reliable data storage and retrieval. The RS Encoder and decoder are designed in structural modeling and develop the hardware.
Prateek Asthana has completed his Ph.D. from the National Institute of Technology (NIT) Hamirpur in 2020. He completed his post-graduation from JSS Academy of Technical Education, Noida in 2014, and his graduation from Amity University, Noida in 2011. His area of research includes front-end and back-end VLSI, MEMS, and energy harvesting.
Number of Pages:
LAP LAMBERT Academic Publishing
Reed solomon, error coding, VHDL, Front End
TECHNOLOGY / Electronics / General